[ CourseLala.com ] Udemy - VSD - Static Timing Analysis - I

磁力链接/BT种子名称

[ CourseLala.com ] Udemy - VSD - Static Timing Analysis - I

磁力链接/BT种子简介

种子哈希：5bbda7ae82b2279d8b5ec457708a872a8cbdcea9
文件大小：572.7M
已经下载：1267次
下载速度：极快
收录时间：2022-04-12
最近下载：2025-06-13

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文件列表

  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/004 Clk-q delay calculation.mp4 40.0 MB
  • ~Get Your Files Here !/01 - Introduction and agenda/006 Introduction to slew, load and clock checks.mp4 38.7 MB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/005 Convert pins to nodes and compute AAT, RAT and slack.mp4 36.2 MB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/006 Jitter extraction and accounting in setup timing analysis.mp4 33.7 MB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/004 Compute slack and introduction to GBA-PBA analysis.mp4 33.5 MB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/003 Library setup time calculation.mp4 32.1 MB
  • ~Get Your Files Here !/01 - Introduction and agenda/005 Introduction to data check and latch timing.mp4 30.9 MB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/002 Compute actual arrival time (AAT).mp4 28.5 MB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/003 Compute required arrival time (RAT).mp4 27.0 MB
  • ~Get Your Files Here !/01 - Introduction and agenda/003 Introduction to required time and slack.mp4 25.8 MB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/001 Convert logic gates into nodes.mp4 24.7 MB
  • ~Get Your Files Here !/01 - Introduction and agenda/004 Introduction to basic categories of setup and hold analysis.mp4 23.7 MB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/005 Steps to create eye diagram for jitter analysis.mp4 22.9 MB
  • ~Get Your Files Here !/01 - Introduction and agenda/002 Introduction to timing path and arrival time.mp4 22.5 MB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/001 Introduction to transistor level circuit for flops.mp4 22.0 MB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/002 Negative and positive latch transistor level operation.mp4 21.7 MB
  • ~Get Your Files Here !/04 - Textual timing reports and hold analysis/001 Setup analysis - graphical to textual representation.mp4 15.2 MB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/001 OCV based setup timing analysis.mp4 15.0 MB
  • ~Get Your Files Here !/05 - On-chip variation/003 Relationship between resistance, drain current and delay.mp4 14.8 MB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/004 Hold timing analysis after pessimism removal.mp4 14.8 MB
  • ~Get Your Files Here !/05 - On-chip variation/001 Sources of variation - etching.mp4 14.1 MB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/002 Setup timing analysis after pessimism removal.mp4 13.9 MB
  • ~Get Your Files Here !/04 - Textual timing reports and hold analysis/002 Hold analysis with real clocks.mp4 11.3 MB
  • ~Get Your Files Here !/05 - On-chip variation/002 Sources of variation - oxide thickness.mp4 10.7 MB
  • ~Get Your Files Here !/04 - Textual timing reports and hold analysis/003 Hold analysis - graphical to textual representation.mp4 8.8 MB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/003 OCV based hold timing analysis.mp4 8.8 MB
  • ~Get Your Files Here !/01 - Introduction and agenda/001 Introduction.mp4 6.4 MB
  • ~Get Your Files Here !/07 - Conclusion/001 Conclusion and next topics!!.mp4 2.6 MB
  • ~Get Your Files Here !/05 - On-chip variation/003 Relationship between resistance, drain current and delay_en.vtt 14.4 kB
  • ~Get Your Files Here !/05 - On-chip variation/001 Sources of variation - etching_en.vtt 13.9 kB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/005 Convert pins to nodes and compute AAT, RAT and slack_en.vtt 13.0 kB
  • ~Get Your Files Here !/04 - Textual timing reports and hold analysis/002 Hold analysis with real clocks_en.vtt 12.9 kB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/001 OCV based setup timing analysis_en.vtt 12.9 kB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/004 Clk-q delay calculation_en.vtt 12.4 kB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/004 Hold timing analysis after pessimism removal_en.vtt 12.2 kB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/001 Convert logic gates into nodes_en.vtt 12.2 kB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/002 Compute actual arrival time (AAT)_en.vtt 12.1 kB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/004 Compute slack and introduction to GBA-PBA analysis_en.vtt 12.1 kB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/002 Setup timing analysis after pessimism removal_en.vtt 12.0 kB
  • ~Get Your Files Here !/01 - Introduction and agenda/004 Introduction to basic categories of setup and hold analysis_en.vtt 11.7 kB
  • ~Get Your Files Here !/01 - Introduction and agenda/002 Introduction to timing path and arrival time_en.vtt 11.5 kB
  • ~Get Your Files Here !/05 - On-chip variation/002 Sources of variation - oxide thickness_en.vtt 11.3 kB
  • ~Get Your Files Here !/01 - Introduction and agenda/005 Introduction to data check and latch timing_en.vtt 11.0 kB
  • ~Get Your Files Here !/01 - Introduction and agenda/003 Introduction to required time and slack_en.vtt 10.9 kB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/003 Library setup time calculation_en.vtt 10.8 kB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/005 Steps to create eye diagram for jitter analysis_en.vtt 10.7 kB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/001 Introduction to transistor level circuit for flops_en.vtt 10.5 kB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/006 Jitter extraction and accounting in setup timing analysis_en.vtt 10.5 kB
  • ~Get Your Files Here !/03 - Clk-to-q delay, library setup, hold time and jitter/002 Negative and positive latch transistor level operation_en.vtt 10.3 kB
  • ~Get Your Files Here !/04 - Textual timing reports and hold analysis/001 Setup analysis - graphical to textual representation_en.vtt 10.2 kB
  • ~Get Your Files Here !/02 - First things first - Introduction to timing graph/003 Compute required arrival time (RAT)_en.vtt 10.2 kB
  • ~Get Your Files Here !/01 - Introduction and agenda/006 Introduction to slew, load and clock checks_en.vtt 10.0 kB
  • ~Get Your Files Here !/04 - Textual timing reports and hold analysis/003 Hold analysis - graphical to textual representation_en.vtt 9.6 kB
  • ~Get Your Files Here !/06 - OCV timing and pessimism removal/003 OCV based hold timing analysis_en.vtt 7.5 kB
  • ~Get Your Files Here !/01 - Introduction and agenda/001 Introduction_en.vtt 3.8 kB
  • ~Get Your Files Here !/07 - Conclusion/001 Conclusion and next topics!!_en.vtt 3.2 kB
  • ~Get Your Files Here !/Bonus Resources.txt 386 Bytes
  • Get Bonus Downloads Here.url 180 Bytes

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